Previously, the most widely used approach for transmitting a first format data on a second format was to use the same approach as in the network hub. However, translation via the data hub port introduces significant data delays, typically in excess of 90 serial data bits, which reduces the network performance and adds to the limitations of the physical size of the network.
Such data delay and other data translation limitations experienced by hub and other prior data translation devices are, in large part, a result of internal transfer data from the incoming media serial format to an internal parallel format for buffering or processing, and back to the serial format for retransmission. The well established building blocks used in many such systems consist of an integrated circuit, e.g. part # DP83223, which provides the necessary electrical signalling and media state, while a second subsequently connected integrated circuit, e.g. part # DP83240, recovers the clock signal from the incoming signal, decodes or descrambles the NRZ, MLT3 or other cipher format encrypted signal and provides a plaintext data signal in a 4-bit parallel standard. The plaintext parallel data is then received by a buffer or processor provided by a variety of integrated circuits. For hub configurations, similar parallel data paths are provided.
As demonstrated by the widespread adherence to the parallel data format by integrated circuit and equipment designers, the limitations imposed on the data flow by the parallel format are generally accepted as unavoidable, and thus the performance of data translation equipment is only marginally improved.